HDL Works IO Checker v2.1 R1

Software, Graphic & Design. April 17, 2011 by SoftSharing.

HDL Works IO Checker v2.1 R1 | 26 Mb

Verifying hundreds of FPGA IO pins between PCB and FPGA in minutes - When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task. On the FPGA side the pins are assigned to the HDL signals that form the toplevel of the logic implemented on the FPGA. On the PCB side the pins have to be connected to the proper net that will connect it to other components on the PCB.

Because implementation of FPGA and PCB is often done in
parallel, the signal names used are not always identical. To make
things even worse, it is often necessary to perform pin swaps to
prevent PCB routing problems. These pin swaps have to be made both
on the FPGA and the PCB. As this is almost always manual work, and
current devices have over 1500 pins, a mistake is easily made

Intelligent Verification
- IO Checker uses rules (based on regular expressions) to match the
signal names in both the FPGA and PCB design environment. It allows
the tool to validate groups of matches although individual signals can
still differ. The rules can be generated automatically and be fine-tuned
by the designer. The automated approach will often match 80% to 90% of
all device pins.

- The flexibility of IO Checker allows it to be used in any design flow
and does not require any design methodology. The rules generator in
combination with the sorted problem view allows engineers to validate
a 1000 pins device in half an hour.

- Once the project and its rules are defined it is a simple task to keep
the FPGA and PCB data consistent. All out-of-date files are processed in
one action and all changes are reported

Home Page - http://www.zc-software.com

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